AR# 40462


MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center Design Assistant - How are CAS Latency (CL) and CAS Write Latency (CWL - DDR3 only) determined?


When generating a MIG 7 Series and Virtex-6 DDR3/DDR2 design, I do not have the option to select the CAS Latency (CL) or CAS Write Latency (CWL - DDR3 only) through the GUI. How are these values determined and where can I view the values selected?

NOTE:This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Based on the memory part and frequency selected through the GUI, MIG selects the appropriate CL and CWL. When generating a custom part, MIG will use the selected base part along with the frequency to determine the appropriate CL and CWL.

To view the CL and CWL values the tool generated, open the example_top.v/.vhd (or <user_design>.v/.vhd for 7 Series designs andmemc_ui_top.v/.vhd module (located in 'rtl/ip_top' directory) for Virtex-6 designs) and locate the CL and CWL parameters.

Modification of these parameters should not be necessary. Ensure the correct base part is chosen for the custom part flow as this will ensure the CL and CWL parameters are set correctly.



Answer Number 问答标题 问题版本 已解决问题的版本
34243 Xilinx Memory Interface Solution Center N/A N/A
AR# 40462
日期 09/18/2012
状态 Active
Type 解决方案中心
器件 More Less
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