AR# 40519


Serial RapidIO v5.6 - Release Notes and Known Issues for ISE Design Suite 13.1


This Release Notes and Known Issues Answer Record is for the Serial RapidIO v5.6 Core, which was released in ISE 13.1 Design Suite and contains the following information:
  • Supported Devices
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tool requirements, see the IP Release Notes Guide:


Supported Devices
  • Virtex-4 XC FX
  • Virtex-5 XC LXT/SXT/TXT/FXT
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Spartan-6 XC LXT
New Features
  • ISE 13.1 Design Suite support
Resolved Issues
  • (Xilinx Answer 35570) PORT_INITIALIZED fails to assert in Virtex-6 1.25 G and 2.5 G cores (CR 576404)
  • (Xilinx Answer 36342) Example design reset module fails to completely reset the buffer (CR 566276)
  • (Xilinx Answer 38132) Virtex-6 MMCM BANDWIDTH attribute incorrect (CR 574172)
  • PHY ignores LREQ received while PHY is issuing a PNA (CR 579364)
  • PHY sometimes issues PR in addition to LRESP after receiving LREQ (CR 575534)
  • (Xilinx Answer 39795) PHY passes corrupted received packets on to buffer interface (CR 580844)
  • (Xilinx Answer 37912) PHY inserts idle sequences before EOP on some transmitted packets (CR 574885)
Known Issues

Revision History:

02/17/2011 - Initial Release
03/01/2011 - Updated for 13.1
09/26/2012 - Added (Xilinx Answer 51958)
12/03/2012 - Added (Xilinx Answer 53260) and (Xilinx Answer 53261)




AR# 40519
日期 12/03/2012
状态 Active
Type 版本说明
器件 More Less
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