Packaging Solution Center

The Packaging Solution Center is available to address all questions related to Packaging.

Whether you are starting with part selection, working on layout and design considerations, or even in the assembly process, use the Packaging Solution Center to guide you to the right information.

To update your Xilinx Alert Notification Preferences, please go to:

http://www.xilinx.com/support/myalerts

设计助手

Packaging Design Assistant

The Packaging Design Assistant outlines packaging related information based different steps in the process, whether trying to select a part or package, compiling design considerations for a board layout, or looking for more info during assembly.

NOTE: This answer record is part of the Xilinx Packaging Solution Center (Xilinx Answer 40687). The Xilinx Packaging Solution Center is available to address all questions related Packaging.


First, select the design phase where you have a question or are troubleshooting an issue related to your configuration solution. This ensures that the Packaging Design Assistant points you to the information you need to continually move forward with your design.

(Xilinx Answer 40691) Part Selection and Ordering: The part markings are further explained here along with material declaration, explanations of stepping, and device specific packaging common questions are all addressed here.
(Xilinx Answer 40690) Layout and Design Considerations: Issues such as temperature design issues, heat sink selection, and flight time for packages are all explained here.
(Xilinx Answer 40689) Assembly Process: The device reliability information, and moisture and information can all be found here.

技术文档

Packaging Solution Center - Documentation

Please refer to the following documentation when using Xilinx Packaging Solutions.

NOTE: This answer record is part of the Xilinx Packaging Solution Center (Xilinx Answer 40687). Xilinx Packaging Solution Center is available to address all questions related to packaging.


Generic Packaging Solutions

Virtex-6

Spartan-6


设计咨询

有关 Virtex-6 FPGA 设计咨询的主要答复记录

设计咨询答复记录是专为对于当前进行中的设计至关重要的问题所创建的,精选后用于赛灵思提醒通知系统。

本设计咨询涵盖了 Virtex-6 FPGA 以及影响 Virtex-6 FPGA 设计的相关问题。


2020 年 4 月 20 日发布的设计咨询

2020 年 4 月 15 日(赛灵思答复记录 73541)7 系列/Virtex-6 FPGA 设计咨询:破解比特流加密。[SECURITY]

2013 年 4 月 8 日发布的设计咨询提醒:

2013 年 4 月 5 日(赛灵思答复记录 45166)更新了有关 Virtex-6 FPGA GTH 收发器的设计咨询,包括更新的 RX_P1_CTRL 属性值

  

2012 年 8 月 13 日发布的设计咨询提醒:

2012 年 8 月 15 日(赛灵思答复记录 51145)设计咨询 - 14.2 iMPACT - 对 Virtex-6 进行间接编程导致工具在无预警的情况下崩溃


2012 年 5 月 21 日发布的设计咨询:

2012 年 5 月 17 日(赛灵思答复记录 47938)有关 Virtex-6 FPGA 的设计咨询:使用 OPAD Tioop/Tiotp 的设计必须重新运行时序分析

  

2012 年 2 月 13 日发布的设计咨询提醒:

2012 年 1 月 25 日更新(赛灵思答复记录 42444)有关 Virtex-6 FPGA 的设计咨询:使用 18K/36K 块 RAM 或 18K/36K FIFO 的设计必须重新运行时序分析

  

2012 年 1 月 16 日发布的设计咨询提醒:

2012 年 1 月 13 日(赛灵思答复记录 45166)有关 Virtex-6 的设计咨询:GTH 收发器启动时突发错误,并且启动时 RXRECCLK 不执行切换

  

2011 年 12 月 19 日发布的设计咨询提醒:

2011 年 12 月 13 日(赛灵思答复记录 43591)更新有关 Virtex-6 FPGA GTH 收发器的设计咨询,解决 RXBUFRESET 相关初始化序列和 BUFFER_CONFIG_LANEx 问题,包含有关工程采样 (ES) 硅片的修复信息

2011 年 11 月 21 日发布的设计咨询提醒:

2011 年 11 月 21 日(赛灵思答复记录 44174)有关启动后正确同步触发器和 SRL 的方法的设计咨询

  

2011 年 9 月 19 日发布的设计咨询提醒:

2011 年 9 月 19 日(赛灵思答复记录 43829)有关 Virtex-6 FPGA GTH 收发器的设计咨询 - x4 模式下封装中出现 RXBUFRESET 连接错误

  

2011 年 8 月 22 日发布的设计咨询提醒:

2011 年 8 月 22 日(赛灵思答复记录 43591)有关 Virtex-6 FPGA GTH 收发器的设计咨询:需更新以解决 RXBUFRESET 相关初始化序列和 BUFFER_CONFIG_LANE -x 问题。

  

2011 年 8 月 8 日发布的设计咨询提醒:

2011 年 8 月 8 日(赛灵思答复记录 43346)有关 Virtex-6 GTH 的设计咨询:非重定时 10G+ 光学接口(例如,SFP+ 和 QSFP)的建议
2011 年 8 月 8 日(赛灵思答复记录 42682)有关 Virtex-6 FPGA 的设计咨询 - 13.x iMPACT - 当目标 FPGA 并非 JTAG 链中的唯一器件时,发生 eFUSE 密钥编程错误

  

2011 年 7 月 11 日发布的设计咨询提醒:

2011 年 7 月 8 日(赛灵思答复记录 42444)有关 Virtex-6 FPGA 的设计咨询:使用 18K/36K 块 RAM 或 18K/36K FIFO 的设计必须重新运行时序分析
2011 年 7 月 7 日(赛灵思答复记录 41821)有关 Virtex-6 FPGA 的设计咨询 - BitGen 选项 -g Next_Config_Addr:默认值已更改
2011 年 7 月 7 日(赛灵思答复记录 41099)有关 Virtex-6 FPGA 的设计咨询:同步 FIFO 的复位必须同步到 RDCLK/WRCLK

  

2011 年 7 月 6 日发布的设计咨询提醒:

2011 年 7 月 1 日(赛灵思答复记录 42444)有关 Virtex-6 FPGA 的设计咨询:使用 18K/36K 块 RAM 或 18K FIFO 的设计必须重新运行时序分析
2011 年 6 月 30 日(赛灵思答复记录 42682)有关 Virtex-6 FPGA 的设计咨询 - 13.x iMPACT - 当目标 FPGA 并非 JTAG 链中的唯一器件时,发生 eFUSE 密钥编程错误
2011 年 4 月 11 日(赛灵思答复记录 41099)有关 Virtex-6 FPGA 的设计咨询:同步 FIFO 的复位必须同步到 RDCLK/WRCLK

  

2011 年 3 月 21 日发布的设计咨询提醒:

2011 年 3 月 18 日(赛灵思答复记录 40885)更新有关 Virtex-6 FPGA 量产级 (Production) GTH 收发器的设计咨询,包含 GTH TXUSERCLKOUT/RXUSERCLKOUT 操作指南。

  

2011 年 3 月 7 日发布的设计咨询提醒:

2011 年 3 月 4 日(赛灵思答复记录 40885)有关 Virtex-6 FPGA 量产级 (Production) GTH 收发器的设计咨询

  

2010 年 10 月 18 日发布的设计咨询提醒:

2010 年 10 月 11 日(赛灵思答复记录 38132)Virtex-6 FPGA MMCM 设计咨询:MMCM BANDWIDTH 属性要求
2010 年 10 月 11 日(赛灵思答复记录 38133)Virtex-6 FPGA MMCM 设计咨询:当 Fclkin > 315 MHz 时的 DIVCLK_DIVIDE 值的限制
2010 年 9 月 27 日(赛灵思答复记录 38134)Virtex-6 配置 PROGRAM_B 管脚在上电前如果被置低就不会延迟配置
2010 年 9 月 7 日(赛灵思答复记录 36642)Virtex-6 系统监控器最大 DCLK 频率已调低至 80 MHz

  

2010 年 8 月 30 日发布的设计咨询提醒:

2010 年 8 月 27 日(赛灵思答复记录 37667)Virtex-6 FPGA -1L 工业级 Vccint 规格更改

  

2010 年 3 月 22 日发布的设计咨询:

2010 年 3 月 19 日(赛灵思答复记录 34859)Virtex-6 FPGA 块 RAM 设计咨询:地址空间重叠
2010 年 2 月 11 日(赛灵思答复记录 33849)Virtex-6 FPGA MMCM 面向所有 MMCM、VCO 最低频率和 CLKBOUT_MULT_F 值的新要求
2010 年 1 月 22 日(赛灵思答复记录 34164)Virtex-6 11.4 ISE - Virtex-6 FPGA 设计在 ISE 11.5 或更高版本的软件中必须重新运行实现

修订历史:


2013 年 4 月 5 日更新答复记录 45166
2012 年 9 月 24 日次要更新:内容无更改
2012 年 8 月 9 日新增答复记录 51145
2012 年 5 月 17 日新增答复记录 47938
2012 年 2 月 13 日新增答复记录 42444 更新
2012 年 1 月 13 日新增答复记录 45166
2011 年 12 月 13 日更新答复记录 43591
2011 年 12 月 12 日更新答复记录 44174 标题
2011 年 11 月 21 日新增答复记录 44174
2011 年 9 月 15 日新增答复记录 43829
2011 年 8 月 18 日新增答复记录 43591
2011 年 8 月 1 日新增答复记录 43346,更新答复记录 42682
2011 年 7 月 7 日新增答复记录 41821,并更新答复记录 42444 和 41099
2011 年 7 月 5 日新增答复记录 42444,更新答复记录 41099
2011 年 6 月 30 日新增答复记录 42682
2011 年 3 月 18 日更新答复记录 40885
2011 年 3 月 4 日新增答复记录 40885
2010 年 10 月 14 日新增答复记录 38134 和 36642
2010 年 10 月 12 日新增答复记录 38132 和 38133
2010 年 8 月 27 日新增答复记录 37667
2010 年 3 月 19 日——初始版本

Answer Number 问答标题 问题版本 已解决问题的版本
45166 Virtex-6 FPGA GTH 收发器 - 信道处于节能模式会导致Quad出现错误 N/A N/A
43829 Design Advisory for Virtex-6 FPGA GTH Transceivers - Incorrect RXBUFRESET connections in the wrapper in x4 mode N/A N/A
42444 Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis N/A N/A
41821 Design Advisory for Virtex-6 BitGen Option Change Can Cause Configuration Failures for Bit Files Generated in 13.2 Where 13.1 Files Worked N/A N/A
41099 Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK N/A N/A
38134 Design Advisory for Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration N/A N/A
38133 Virtex-6 FPGA MMCM 设计建议- 当 Fclkin > 315 MHz 时限定 DIVCLK_DIVIDE 的值 N/A N/A
38132 Virtex-6 FPGA MMCM 设计咨询 - MMCM BANDWIDTH 属性要求 N/A N/A
37667 Virtex-6 FPGA -1L 工业级 Vccint 规范修改 N/A N/A
34859 Virtex-6 FPGA Block RAM 设计咨询 - 地址空间重叠 N/A N/A
47938 有关 14.1 时序分析 Virtex-6 的设计咨询——Tioop/Tiotp 值在分析 OFFSET OUT 和 FROM:TO 约束时有所增加 N/A N/A
44174 设计咨询 - 在启动后正确同步化SRL与触发器的技巧 N/A N/A
33849 Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values N/A N/A
34164 Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software N/A N/A
51145 设计咨询 - 14.2 iMPACT - 对 Virtex-6 进行间接编程导致工具在无预警的情况下崩溃 N/A N/A

Design Advisory Master Answer Record for Spartan-6 FPGA

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. This answer record lists the Design Advisories that have been communicated for the Spartan-6 FPGA products.

For a complete list of Known Issues for Spartan-6 FPGAs, please see (Xilinx Answer 40000) for ISE Design Suite 13.x and (Xilinx Answer 35180) for ISE Design Suite 12.x.

Design Advisory Alerted on June 19, 2013
06/13/2013 - (Xilinx Answer 56363) - Design Advisory for Spartan-6 FPGAs - JTAG Boundary Scan testing can fail with inverted values seen on pins when the device is configured

Design Advisory Alerted on June 10, 2013
06/06/2013 - (Xilinx Answer 56113) - Design Advisory for Spartan-6 BUFIO2, DIVIDE = 2 Issue

Design Advisory Alerted on April 02, 2013
03/28/2013 - (Xilinx Answer 55037) - Design Advisory for Spartan-3A and Spartan-6: After SelectMAP configuration, when Readback CRC is enabled and an ABORT is triggered spurious failures may be flagged in Readback CRC

Design Advisory Alerted on November 19, 2012:
11/15/2012 - (Xilinx Answer 52716) - Design Advisory for Spartan-6 FPGAs - Configuration Readback including SEM_IP or POST_CRC causes power distribution network noise affecting SelectIO and GTP interfaces

Design Advisory Alerted on February 13, 2012:
02/10/2012 - (Xilinx Answer 46141) - Design Advisory for Spartan-6 - PLL CLKOUT3 Incorrect Phase Shift

Design Advisory Alerted on December 12, 2011:
12/5/2011 - (Xilinx Answer 45011) - Design Advisory for Spartan-6 - BUFPLL LOCK output always high in Bank 2

Design Advisory Alerted on November 21, 2011:
11/21/2011 - (Xilinx Answer 44174) - Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup

Design Advisories Alerted on November 7, 2011:
11/07/2011 - (Xilinx Answer 44192) - Design Advisory for Spartan-6 FPGA Speed File - Updates for Block RAM fMAX in Lower Power -1L Devices
11/07/2011 - (Xilinx Answer 44193) - Design Advisory for Spartan-6 FPGA Speed File - Updates for DCM Phase Alignment

Design Advisories Alerted on September 26, 2011:
09/26/2011 - (Xilinx Answer 44192) - Design Advisory for Spartan-6 FPGA Speed File - Updates for Block RAM fMAX in Lower Power -1L Devices
09/26/2011 - (Xilinx Answer 44193) - Design Advisory for Spartan-6 FPGA Speed File - Updates for DCM Phase Alignment

Design Advisory Alerted on July 11, 2011:
07/07/2011 - (Xilinx Answer 39999) - Design Advisory for Spartan-6 - 9K Block RAM Initialization Support

Design Advisories Alerted on April 18, 2011:
04/18/2011 - (Xilinx Answer 41520) - Design Advisory for Spartan-6 MCB - Removal of VCCINT restrictions to reach maximum DDR3 data rates
04/18/2011 - (Xilinx Answer 41083) - Design Advisory for Spartan-6 IODELAY2 - IODELAY2 Data Rate and Corresponding Bit Error Rates for New Mask Revision Silicon

Design Advisory Alerted on April 04, 2011:
04/04/2011 - (Xilinx Answer 41356) - Design Advisory for Lower Power Spartan-6 -1L Speed Grade - IODELAY2 Support Restricted to Tap 0

Design Advisories Alerted on March 01, 2011:
03/01/2011 - (Xilinx Answer 40387) Design Advisory for Spartan-6 Configuration - GCLK0 input can glitch at the end of configuration
02/23/2011 - (Xilinx Answer 40818) Design Advisory for Spartan-6 SelectIO - INTERM_XX not being appropriately turned on in BitGen for Spartan-6 FPGA inputs

Design Advisory Alerted on December 13, 2010:
12/13/2010 - (Xilinx Answer 39582) Design Advisory for Spartan-6 - When using POST_CONFIG_CRC the INIT_B pin can not be User I/O

Design Advisory Alerted on November 15, 2010:
11/11/2010 - (Xilinx Answer 38733) Design Advisory for Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction

Design Advisories Alerted on October 18, 2010:
10/13/2010 - (Xilinx Answer 38408) Design Advisory for Spartan-6 - IODELAY2 - early edge delays, late edge delays, and single data bit corruption
10/14/2010 - (Xilinx Answer 35881) Design Advisory for 12.2 Timing/Spartan-6 - DRAM/RAMB instance not analyzed under PERIOD/FROM:TO constraint (Not added to timegroups using TNM)

Design Advisory Alerted on July 19, 2010:
07/19/2010 - (Xilinx Answer 35237) Design Advisory for Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines

Design Advisories Alerted on June 14, 2010:
06/14/2010 - (Xilinx Answer 35978) Design Advisory for MIG Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs
06/14/2010 - (Xilinx Answer 35976) Design Advisory for MIG Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality - SW / IP update required
06/14/2010 - (Xilinx Answer 35818) Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 and DDR3 interfaces

Design Advisory Alerted on April 26, 2010:
04/20/2010 (Xilinx Answer 35237) Design Advisory for Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines

Design Advisory Alerted on March 29, 2010:
3/25/2010 (Xilinx Answer 34712) Design Advisory for Spartan-6 FPGA Block RAM - 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect

Design Advisories Alerted on March 22, 2010:
03/19/2010 (Xilinx Answer 34541) Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM SDP Port Width Restriction
03/19/2010 (Xilinx Answer 34533) Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap

Revision History

06/14/13 - Added 56363
06/06/13 - Added 56113
03/28/13 - Added 55037
11/15/12 - Added 52716
02/10/12 - Added 46141
12/12/11 - Updated title for 44174
12/05/11 - Added 45011
11/21/11 - Added 44174
11/07/11 - Updated 44192 and 44193
09/26/11 - Added 44192 and 44193
07/15/11 - Minor formatting changes
07/11/11 - Added 39999
04/18/11 - Adding 41520 and 41083, also link to 40000 for ISE software 13.1 Known Issues
04/04/11 - Adding 41356
03/01/11 - Added 40387 and 40818
12/13/10 - Added 39582
11/15/10 - Added 38733
10/15/10 - Added 38408 and 35881
07/16/10 - Added 35237
06/14/10 - Added 35978, 35976, and 35818
05/24/10 - Added 35180 for ISE software 12.1 Known Issues
04/26/10 - Added 35237
03/25/10 - Added 34712
03/24/10 - Minor format change
03/22/10 - Initial release 34541 and 34533


Answer Number 问答标题 问题版本 已解决问题的版本
45011 Spartan-6 设计咨询 - Bank 2 中的 BUFPLL LOCK 输出始终处于高电平状态 N/A N/A
41356 Design Advisory for Lower Power Spartan-6 -1L Speed Grade - IODELAY2 Support Restricted to Tap 0 N/A N/A
41083 Design Advisory for Spartan-6 IODELAY2 - IODELAY2 Data Rate and Corresponding Bit Error Rates for New Mask Revision Silicon N/A N/A
39999 Spartan-6 FPGA 设计咨询 - 9K Block RAM 初始化支持 N/A N/A
39582 Spartan-6 的设计咨询 - 在使用 POST_CONFIG_CRC 时,INIT_B 引脚不能为 User I/O N/A N/A
38733 Design Advisory for Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction N/A N/A
38408 Spartan-6 IODELAY2 设计咨询 - 后期和早期边缘延迟 以及单个数据位损坏 N/A N/A
35881 Design Advisory for 12.2 Timing/Spartan-6 - DRAM/RAMB instance not analyzed under PERIOD/FROM:TO constraint (Not added to timegroups using TNM) N/A N/A
34712 Design Advisory for Spartan-6 FPGA Block RAM - 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect N/A N/A
40818 Spartan-6 SelectIO 设计咨询 — INTERM_XX 未能在 Spartan-6 FPGA 输入的 BitGen 中正确开启 N/A N/A
40387 Design Advisory for Spartan-6 Configuration - GCLK0 input can glitch at the end of configuration N/A N/A
44174 设计咨询 - 在启动后正确同步化SRL与触发器的技巧 N/A N/A
41520 面向 Spartan-6 MCB 的设计咨询 - 取消 VCCINT 限制以达到最大 DDR3 数据速率 N/A N/A
35818 Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 Interfaces N/A N/A
34533 Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap N/A N/A
34541 Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM Simple Dual Port (SDP) Data Width Restriction N/A N/A
55037 Design Advisory for Spartan-3A and Spartan-6 - After SelectMAP configuration, when Readback CRC is enabled and an ABORT is triggered, spurious failures might be flagged in Readback CRC N/A N/A
56113 Spartan-6 BUFIO2, DIVIDE 设计咨询= 第 2 版 N/A N/A
56363 Spartan-6 FPGA 设计咨询 — 如果在配置器件时引脚上出现逆变值,JTAG 边界扫描测试就可能失败。 N/A N/A