AR# 40977


12.x Place - "ERROR:Place:909 - Regional Clock Net "xxx" cannot possibly be routed to component "xxx" "


The following error is reported during MAP:

ERROR:Place:909 - Regional Clock Net "clock_name" cannot possibly be routed to component "comp_name" (placed in
clock region "CLOCKREGIONP_X1Y2"), since it is too far away from source BUFR "bufr_name" (placed in clock region
"CLOCKREGION_X0Y2"). The situation may be caused by user constraints, or the complexity of the design. Constraining
the components related to the regional clock properly may guide the tool to find a solution.
To debug your design with partially routed results, please allow map/placer to finish the execution (by setting
environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).

How can I resolve this issue?


This error indicates that the component driven by the Regional Clock Net (BUFR output) is placed in a clock region that cannot be reached by this clock net. 

To resolve this problem, try the following:

1. Try different MAP/PAR options.

2. Evaluate if the BUFRs in certain clock regions are not sufficient for the design leading to the BUFR being placed far away from the source/destination.

3. Apply an area_group constraint to the load components of the regional clock net.

This will limit these components to being placed in the clock regions which the clock net can reach.

(Refer to the target device user guide for information on BUFR structure.)

net "clock_name" TNM_NET = group1;

TIMEGRP "group1" AREA_GROUP =group2;


4. This issue can also happened in MIG/MPMC designs if you assign/modify the pin locations without MIG's update and verify. 

Going back through the entire MIG flow can solve this problem.

AR# 40977
日期 03/24/2015
状态 Active
Type 错误信息
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