The MIG 7 Series Release Notes and Known Issues have been combined into a single answer record for ease of viewing. Please visit (Xilinx Answer 45195).
This Release Note and Known Issues Answer Record is for the Memory Interface Generator (MIG) 7 Series 1.2 released in ISE Design Suite 13.2 and contains the following information:
For installation instructions, general CORE Generator known issues, and design tools requirements, see theIP Release Notes Guide (XTP025).
General InformationFor a list of supported memory interfaces and features for 7 Series FPGAs, see:
(Xilinx Answer 42665) MIG 7 Series v1.2 - Why does the MIG Example Design fail in BitGen?
(Xilinx Answer 42836) MIG 7 Series v1.2 - Incorrect PHASER IN and PHASER OUT constraints generated for compatible Artix-7 device
(Xilinx Answer 42678)13.2 BitGen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"
(Xilinx Answer 42811) MIG 7 Series v1.2 - Setup error on PHY Hard blocks due to incorrect timing model
(Xilinx Answer 42808) MIG 7 Series v1.2 - Component Switching Limit Error on PHY Hard blocks due to incorrect timing model.
(Xilinx Answer 42831) MIG 7 Series v1.2 DDR3/QDRII+/RLDRAM II - design fails in core generation with single-ended system clock
(Xilinx Answer 43250) MIG 7 Series v1.1-v1.2 DDR3/DDR2 - Internal VREF constraint is not applied across all memory banks
(Xilinx Answer 44019) MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL = "OFF" is supported for hardware only and not behavioral simulation
(Xilinx Answer 43908) MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL" option is not documented in UG586
DDR3 SDRAM Memory Interface Designs
(Xilinx Answer 42832) MIG 7 Series v1.2 DDR3 - FULL calibration mode violates tREFI requirement
(Xilinx Answer 42833) MIG 7 Series v1.2 DDR3 - Parity error for RDIMM designs during memory initialization and calibration process
(Xilinx Answer 42834) MIG 7 Series v1.2 DDR3 - tIH and tIS violation on CKE and ODT pins for DDR3 SDRAM designs during simulation
(Xilinx Answer 41981) MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Ctrl pins should be limited to a single bank
(Xilinx Answer 42559) MIG 7 Series v1.1-v1.2 DDR3 SDRAM - additional hard block constraints are incorrectly generated when the reset_n pin is moved to a different bank for a multi-controller design.
(Xilinx Answer 42036) MIG 7 Series v1.1-v1.2 DDR3 - Internal/External VREF Guidelines
(Xilinx Answer 44527) MIG 7 Series v1.2 DDR3 - Minimum Vccint of 1.0V requirement to achieve 1600 Mbps performance
RLDRAM II Memory Interface Designs
(Xilinx Answer 42725)MIG 7 Series v1.2 - No CC pair available for System Clock
QDRII+ SRAM Memory Interface Designs
(Xilinx Answer 42726) MIG 7 Series v1.1-v1.2 QDRII+ - Model name is incorrect in sim.do for Cypress x36 component
(Xilinx Answer 42729) MIG 7 Series v1.1-v1.2 QDRII+ - Custom x36 memory part showing the wrong data width
(Xilinx Answer 42730) MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in ".veo"