AR# 41923

MIG v3.61 Virtex-5 DDR2 - MT47H512M8 generates incorrect COL_WIDTH

描述

When I look at the HDL in my MIG design, I see that the COL_WIDTH parameter is set to 11 when it should be set to a value of 10.

parameter COL_WIDTH = 11, // # of memory column bits.

解决方案

To work around the problem, set the top-level parameter "COL_WIDTH" to a value of 10. This should be set in sim_tb_top.v/vhd for simulation and <design_name>.v/vhd for implementation and hardware.

If this is a multi-controller design, then the parameter will be called C#_DDR2_COL_WIDTH.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 41923
日期 05/20/2012
状态 Active
Type 已知问题
器件 More Less
Tools
IP