AR# 42642


AXI Bridge for PCI Express - AXI Interconnect frequency cannot be determined when using the axi_aclk_out clock


Version Found: 1.00.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

The interconnect frequency might issue one of the following warning or information messages listed below when the axi_aclk_out clock is clocking the interconnect:

INFO:EDK:740 - Cannot determine the input clock associated with port :axi_pcie_0:axi_aclk_out. Clock DRCs will not be performed on this core and cores connected to it.

INFO:EDK:1039 - Did not update the value for parameter:axi_pcie_0:C_AXI_ACLK_FREQ_HZ. Top-level frequency could not be propagated to this IP. Please make sure that you have specified the frequency of the top-level clock port, and that the clocks are properly connected.

WARNING:EDK:3712 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_0 -Frequency of the interconnect's clock port could not be determined. All IPsin the design will be considered to be asynchronous with respect to the interconnect. This will lead to more resource usage. You can avoid this by specifying the clock frequency on the port that the interconnect's clock is connected to.

Note: The "Version Found" column lists the version that the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


This is a known issue with the AXI Bridge for PCI Express caused by a combination of two known issues:

  • The util_ds_buf not propagating the reference frequency information to the bridge's refclk port. This is currently still a known restriction and is not planned to be fixed due to restrictions on the util_ds_buf pcore. For this reason, step #1 will need to still be implemented.
  • The axi_out_clk not containing the correct CLK_FACTOR in the MPD. This issue is fixed according to (Xilinx Answer 44969)

To work around this problem, follow these steps:

  1. Bring the util_ds_buf local and modify the MPD as shown below:

    PORT IBUF_DS_P = "", DIR = I, VEC = [0:(C_SIZE-1)], SIGIS = CLK
    PORT IBUF_DS_N = "", DIR = I, VEC = [0:(C_SIZE-1)], SIGIS = CLK

  2. Bring the axi_pcie local and modify the MPD and Tcl file located in the data
    • For the MPD file, add a new parameter called:


      Also, modify one of the axi_aclk_out ports as follows:

      PORT axi_aclk_out = "", DIR = O, SIGIS = CLK, BUS = M_AXI:S_AXI, CLK_INPORT = REFCLK, CLK_FACTOR = 1.0 * C_AXI_ACLK_FREQ_HZ / (1.0 * REF_CLK_FREQ_HZ)

    • For the Tcl file, add the following:

      proc update_aclk_out {param_handle} {
      set mhsinst [xget_hw_parent_handle $param_handle]

      set ref_clk_freq [xget_hw_parameter_value $mhsinst "C_REF_CLK_FREQ"]
      if { $ref_clk_freq == 0 } {
      set ref_clk_freq_hz 100000000
      } elseif { $ref_clk_freq == 1 } {
      set ref_clk_freq_hz 125000000
      } elseif {$ref_clk_freq == 2} {
      set ref_clk_freq_hz 250000000
      } else {
      set ref_clk_freq_hz 100000000
      return $ref_clk_freq_hz

Revision History
04/07/2012 - Additional info on what is fixed
02/02/2011 - fixed a typo
11/21/2011 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 42642
日期 06/06/2013
状态 Active
Type 已知问题
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