描述

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

You can generate aSpartan-6 FPGA MCB MIG design in either VHDL or Verilog to support both XST and Synplicity for synthesis and ISIM and ModelSim for simulation.

For steps on generating a core under the supported CORE Generator options, please see the "Getting Started" sectionsin the Spartan-6 FPGA Memory Interface Solutions User Guide (UG416) and the "DDR2 and DDR3 SDRAM Memory interface Solution in the Virtex-6 FPGA Memory Interface Solutions User Guide (UG406).

If you are targeting Synplify Pro, ensure that you select Synplicity in the CORE Generator Project Options.The RTL and project files generated by MIG will be different based on this selection.

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