2. 技术支持
  3. AR# 4376: FPGA Express: How to assign standard logic vectors as Hex or Octal values
  4. AR# 43768: Design Advisory Master Answer Record for Spartan-6 FPGA SP605 Evaluation Kit

AR# 43768

Design Advisory Master Answer Record for Spartan-6 FPGA SP605 Evaluation Kit

描述

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System: http://www.xilinx.com/support/myalerts.

This Design Advisory covers the Spartan-6 FPGA SP605 Evaluation Kit including critical issues with the reference design delivered with the kit.

解决方案

(Xilinx Answer 34093) - Design Advisory for SP605 - Change to resistor network values on the MGT_AVCC rail

Revision History
09/25/2012 - Minor update; no change to content
09/13/2011 - Minor edit to title
08/09/2011 - Initial Release with Answer Record 34093

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
43987 Xilinx 开发板与套件解决方案中心 - 设计咨询 N/A N/A
AR# 43768
日期 09/25/2012
状态 Active
Type 设计咨询
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