AR# 44487

描述

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Chroma Resampler Core.

The following information is listed for each version of the core:

• New Features
• Bug Fixes
• Known Issues

LogiCORE IP Chroma Resampler Lounge:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-chrom-resamp.html

解决方案

• (Xilinx Answer 34828) How do I simulate my Video IP pCore in EDK?

• Initial release in ISE 14.3 and Vivado 2012.3 tools

• All 7 series
• All Virtex-6
• All Spartan-6

• All 7 series

• ISE 14.3 tool support
• Fixed clock domain issues with registers in the AXI4-Lite connection

• (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

• (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

• Initial release in ISE 14.2 and Vivado 2012.2 tools

• All 7 series
• All Virtex-6
• All Spartan-6

• All 7 series

• ISE 14.2 tool support
• Added s_axi_aclk, s_axi_aclken, s_axi_aresetn to AXI4-Lite interface

• N/A

• (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• Initial release in ISE 14.1 and Vivado 2012.1 tools

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000
• Virtex-6
• Spartan-6

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000

• ISE 14.1 tool support
• AXI4-Stream data interfaces
• Optional AXI4-Lite control interface
• Built-in, optional bypass and test-pattern generator mode
• Built-in, optional throughput monitors
• Supports spatial resolutions from 32x32 up to 7680x7680
• Supports 1080P60 in all supported device families
• Supports 4kx2k @ 24 Hz in supported high performance devices
• Supports up to 24 horizontal filter taps 

• N/A

• N/A

• Initial release in ISE Design Suite 13.3

• Virtex-7
• Kintex-7
• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Spartan-6 XC LX/LXT
• Spartan-6 XA LX/LXT
• Spartan-6 XQ LX/LXT

• ISE 13.3 tool support
• Support for:
  • High-definition (1080p60) resolutions
  • Up to 4095 total scan lines and 4095 pixels per scan line
• Converts between YCbCr:
  • 4:4:4
  • 4:2:2
  • 4:2:0
• Supports both progressive and interlaced video
• Static, predefined, powers-of-two coefficients for low-footprint applications
• Configurable filters sizes with programmable filter coefficients for high performance applications
• Selectable processor interface
  
  • EDK pCore
  • General Purpose Processor
  • Constant Interface
• Support for 8-, 10-, or 12-bit input and output precision
• Xilinx Streaming Video Interface (XSVI) bus simplifies connecting to other video IP

• N/A

• N/A

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