AR# 44529

MIG 7 Series v1.3 DDR3 - Incorrect MAP Parameters when CKE and ODT Are Allocated to a Byte Group Separate from the Remaining Address/Control Signals (ERROR:Route:471)

描述

The MIG v1.3 DDR3 SDRAM design generates the MAP parameters incorrectly when CKE and ODT are allocated to a byte group separate from the remaining address/control signals leading to routing failures during implementation. This issue only occurs when the Debug option is enabled in the MIG tool.This occurs because the routing tools are trying to place debug logic in the CKE/ODT byte group slices. The implementation tools error with a message similar to the following:

"ERROR:Route:471 -
This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be routed:
Unrouteable Net:u_mig_7series_v1_3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_encalib<1>
Unrouteable Net:u_mig_7series_v1_3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_encalib<0>
Unrouteable Net:u_mig_7series_v1_3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable
Unrouteable Net:u_mig_7series_v1_3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phaser_ctl_bus<1>"

解决方案

To work around this issue,you need to change the BYTE_LANES_Bx parameter from '1' to '0' for the byte lane in which CKE and ODT are allocated.

As an example, data byte groups are allocated in Bank #34 and Address in Bank #33 (T0, T1 are allocated for Address and Control signals and in T2 only CKE and ODT are allocated). In this case, MIG generates BYTE_LANES_B1 parameter with the value as 4'b1110. This parameter needs to change to 4'b1100.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A
AR# 44529
日期 05/22/2012
状态 Active
Type 已知问题
器件
IP