AR# 44854

MIG 7 Series v1.3 DDR3 - Certain configurations cause designs to fail calibration in simulation

描述

In certain configurations, MIG 7 Series v1.3 DDR3 SDRAM designs stick in calibration during simulations for all scenarios with "Phy to Controller Clock Ratio" of 1 (nCK_PER_CLK = 2), and also in certain cases for "Phy to Controller Clock Ratio" of 4 (nCK_PER_CLK = 4). These problems could affect hardware simulations and is a result of an issue in one of the RTL parameters.

解决方案

To fix the issue, the PHY_DISABLE_SEQ_MATCH parameter needs to change from "FALSE" to "TRUE" in the ddr_mc_phy_wrapper module located in <component name>/user_design/rtl/phy folder.

This is scheduled to be fixed in the 13.4 MIG v1.4 release.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A
AR# 44854
日期 05/22/2012
状态 Active
Type 已知问题
器件
IP