General Information
The MIG Virtex-6 and Spartan-6 v3.91 products are available through the ISE Design Suite 13.4. For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA Memory Controller Block (MCB), see the following user guides:
For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the following documentation:
For general design and troubleshooting information on MIG, see (Xilinx Answer 34243) for the Xilinx MIG Solution Center.
Software Requirements
New Features
Resolved Issues
Known Issues
Virtex-6
Spartan-6
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
45765 | MIG v3.91 Virtex-6 DDR3/DDR2 - 72-bit and 144-bit AXI Lite designs fail in simulation using ModelSim | N/A | N/A |
47721 | MIG v3.91 Virtex-6 QDRII+ - Initialization sequence incorrect for Cypress parts | N/A | N/A |