AR# 45194


MIG Virtex-6 and Spartan-6 v3.91 - Release Notes and Known Issues for ISE Design Suite 13.4


This Release Notes and Known Issues Answer Record is for the Memory Interface (MIG) v3.91 release in the ISE Design Suite 13.4 and contains the following information:
  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.


General Information

The MIG Virtex-6 and Spartan-6 v3.91 products are available through the ISE Design Suite 13.4. For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA Memory Controller Block (MCB), see the following user guides:

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the following documentation:

For general design and troubleshooting information on MIG, see (Xilinx Answer 34243) for the Xilinx MIG Solution Center.

Software Requirements

New Features

  • ISE Design Suite 13.4 software support

Resolved Issues

Known Issues


  • (Xilinx Answer 44896) MIG v3.7-v3.9 Virtex-6 LXT DDR3 - MMCM_ADV_BANDWIDTH is incorrectly set to "LOW" in top-level module
  • (Xilinx Answer 38731) MIG v3.5-v3.91, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design
  • (Xilinx Answer 39423) MIG v3.6-v3.91 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/Os which require another bank for DCI Cascade
  • (Xilinx Answer 45765) MIG v3.91 Virtex-6 DDR3/DDR2 - 72-bit and 144-bit AXI Lite designs fail in simulation using ModelSim
  • (Xilinx Answer 47721) MIG v3.91 Virtex-6 QDRII+ - Initialization sequence incorrect for Cypress parts


  • (Xilinx Answer 38623) MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mb/s?




AR# 45194
日期 02/20/2013
状态 Active
Type 版本说明
器件 More Less
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