Version Found: 1.00.a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)
The AXI EP Bridge for PCI Express generates 64-bit TLPs when the address lies below a threshold of 4GB.
This is a violation of the PCI Express Specification defined in section 18.104.22.168. When the requested address lies below the 4GB threshold, TLPs should be 32-bit TLPs.
Note: The "Version Found" column lists the version that the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
This is a known issue with the AXI Bridge for PCI Express.
To work around the problem, make sure that you are specifying a range above 4GB by having at least one of the bits set from the C_AXIBAR2PCIEBAR_#U register.