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AR# 45588

MIG 7 Series DDR3/DDR2 - Validating Pin Selection fails on CKE and ODT placement


Starting with MIG 7 series v1.4, the MIG tool now follows the following placement requirements for ODT and CKE as noted in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586):

  • CKE and ODT must be in an address/control byte lane just like all other address/control pins; they cannot be in a data byte lane.
  • CKE and ODT (or any other address/control pin) can be placed on the two pins in a bank that are not within one of the T0, T1, T2, or T3 byte groups (this includes the VRN/VRP pin locations for HP banks and the top or bottom pins of fully bonded HR banks) if ALL of the following conditions are met:
    • The pins are not used for some other function (for example, VRN/VRP pins of an HP bank are not being used for the DCI reference because either DCI cascade or external terminations are implemented).
    • AND the adjacent byte group (T0 or T3) is used as an address/control byte group.
    • AND one of the pins in that adjacent T0 or T3 byte group is either unused, a CK memory clock output, or an external VREF connection.

All existing 7 series MIG DDR3 or DDR2 designs need to be evaluated based on new MIG pin-out rules for the CKE and ODT signals.Previously, there were very few restrictions on the placement of these two signals.However, recently completed analysis shows possible timing issues (setup and hold violations) with the CKE and ODT implementation used by MIG in 13.3 and prior releases. A new CKE and ODT implementation where the signals are treated identically to the remaining Address/Control signals is required to remove timing issues. This new implementation prevents certain CKE and ODT pin assignments that were allowed by MIG in 13.3 and prior releases.

For many DDR3/DDR2 interface configurations generated by prior versions of MIG, the default pin assignments were already in compliance with the new pin-out rules. However, MIG was not checking against the new rules and might have violated them in some cases, so it is important to verify all existing designs. Existing designs found to be violating the new rules will require a board spin.


Action Required:

The ISE 13.4 softwarerelease of MIG will incorporate the new rules and RTL code for CKE and ODT.All existing MIG designs MUST upgrade to 13.4 to ensure compliance to the new pin-out rules and to receive the new RTL code that eliminates the possible timing issues.Note thatthe timing issues are related to the ODT/CKE implementation in MIG in 13.3 and prior releases. Therefore, regardless of the whether a pin-out violates or adheres to the new CKE/ODT rules, updated RTL code is required. Additionally, all new designs should be implemented with the 13.4 or later release. ISE Design Suite 13.4 will be available on January 18, 2012.

If you have any questions regarding the new rules, or require assistance in verifying compliance of an existing pin-out, please open aWebCaseand attach the UCF file and "mig.prj" for analysis.



Answer Number 问答标题 问题版本 已解决问题的版本
45633 关于 7 系列 MIG DDR3/DDR2 设计咨询 - 针对 CKE 和 ODT 的更新引脚布局规则;必须验证现有的 UCF N/A N/A
AR# 45588
日期 12/15/2012
状态 Active
Type 综合文章
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series