This is a valid DRC error . The address bit 15 is only used in cascadable block RAM. The valid addresses for non-cascadable block RAM are only found on pin 14 to (15 - address width). The remaining pins , including pin 15, should be tied High. Please refer page 29 and 37 of the following user guidetofind more information on the DRC.
http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
| AR# 45761 | |
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| 日期 | 12/15/2012 |
| 状态 | Active |
| Type | 综合文章 |
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| Tools |
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