UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. 灵活应变的智能
  2. 技术支持
  3. AR# 45764: MIG 7 Series QDRII+/RLDRAMII - create_ise.bat/.sh fails when Debug Port is Disabled

AR# 45764

MIG 7 Series QDRII+/RLDRAMII - create_ise.bat/.sh fails when Debug Port is Disabled

描述

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

When generating the MIG 7 Series IP core, the chk_win_top and chk_win_pi debug modules are generated even if the Debug Port is disabled in the MIG GUI.

解决方案

This will cause the create_ise.bat/.sh to fail when run since the chk_win_top and chk_win_pi modules are generated and added to the ISE project file. Implementation will also fail since both modules appear in the top-level of the design.

Workaround:

Open "set_ise_prop.tcl" and remove the following two lines:

xfile add "../rtl/chk_win_pi.v"
xfile add "../rtl/chk_win_top.v"

There is no problem if the MIG IP is generated with the Debug Port Enabled or if the ISE project is created manually by the user.
AR# 45764
日期 10/15/2012
状态 Active
Type 已知问题
器件
  • Kintex-7
  • Artix-7
  • Virtex-7
IP
  • MIG 7 Series

通过使用本网站，本人接受使用 cookies。   了解更多

的页面