This signal can be commented out in the UCF file to prevent any implementation errors, and can be safely removed from the design.
If the signal is not removed, the following warning occurs during BitGen:
WARNING:PhysDesignRules:367 - The signal <qdriip_qvld<0>_IBUF> is incomplete. The signal does not drive any load pins in
the design.
The QVLD signal is removed from the MIG QDRII+ design in the 14.1 software release.
| AR# 46020 | |
|---|---|
| 日期 | 08/13/2014 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 |
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| Tools |
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| IP |
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