We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46069

System Generator for DSP v13.4 - Why am I receiving an exception message with the FIR Compiler v6.3?


Why am I receiving the following exception messagewith System Generator for DSP v13.4working with FIR Compiler v6.3:

"Error 0001:

Reported by:

'sysgenDDC_v63_filter/DDC/G(z) Polyphase Decimator 2:1/2 Channel Decimate by 2 MAC FIR /FIR Compiler 6.3 1'


External Model firv6_3_CModel:firv6_3_cmodel threw std::exception:

An error occurred during HDL compilation. WARNING:HDLCompiler:746



Line 751: Range is empty (null range)"


This problem can arise when the hierarchical name of the FIR 6.3 block present in the model contains certain special character(s).

Forexample, in the SysGen demo "SysgenDDC.mdl", the hierarchy is:

sysgenDDC/DDC/G(z) Polyphase Decimator 2:1/2 Channel Decimate by 2 MAC FIR /FIR Compiler 6.3

In the above example, the offending special characters are the parentheses (, ), and the colon ':'.

To work around this issue, rename thetop-module, subsystems, etc., to ensure the hierarchical-name of the FIR 6.3 block does not contain special characters such as:(,),{,},[,],:,^,$,*.

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).



AR# 46069
日期 08/03/2012
状态 Active
Type 已知问题
  • ISE Design Suite - 13.4