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AR# 46268

LogiCORE IP JESD204 v1.1 - What does rxsync signal represent and when does this signal go High?


Forthe LogiCORE IP JESD204 v1.1, what does rxsync signal represent and when does this signal go High?


The rxsync signal represents the synchronization request(sync~) signal from the specification. The 4-bits of the SYNC~ signal give us byte resolution (it is a 32-bit datapath). These signals could be ORedtogether to produce a 1-bit SYNC~ signal.

In JESD204A and JESD204B subclass0 and 2 devices, SYNC~ will go High when all lanes have received valid K28.5s so that their code group synchronization state machines are out of state CS_ININ (section 7.1 in the JESD204 specification).

For JESD204B subclass 1 devices, it will go High on the first local multiframe clock(LMFC) crossing after a SYSREF pulse is received at the FPGA, providing valid K28.5s are received as before (section 6.3 of the specification has more details on this topic).

ForLogiCORE IP JESD204Release Notes from other versions, see(Xilinx Answer 44405).



Answer Number 问答标题 问题版本 已解决问题的版本
44405 LogiCORE IP JESD204 - 发布说明和已知问题 N/A N/A
AR# 46268
日期 12/15/2012
状态 Active
Type 综合文章