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AR# 46273

AXI Bridge for PCI Express - Kintex-7 simulation will not link train when C_PCIE_USE_MODE = 1.0 (IES)

Description

Version Found: 1.02.a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

The AXI Bridge for PCI Express will not link train in simulation when using the pre-compiled libraries from the Xilinx Compilation Library Wizard (compxlib) and the C_PCIE_USE_MODE parameteris set to 1.0. The C_PCIE_USE_MODE parameter needs to be set to 1.0 when targeting Initial Engineering Sample (IES) silicon. Thebridge will get stuck in the Detect state of the Link Training Status State Machine in either the endpoint or root complex configuration in simulation. It will link train properly in hardware.

解决方案

This is a known issue with how the AXI Bridge for PCI Express is compiled by compxlib. The axi_enhanced_pcie_v#_0#_a library needs to compile all the modules with the "SIMULATION" compiler directive defined. Instead of compiling the enhanced library again, follow the instructions below to work around this issue.

Simgen is the tool that creates the simulation files in the "simulation/behavioral" directory. Before running Simgen, modify the MHS so that theC_PCIE_USE_MODEparameter is set to 3.0. When setting C_PCIE_USE_MODEto 3.0, the generated simulation files will be for General Engineering Sample (GES) silicon; however, for simulation purposes the functionality of the bridge will remain the same.

Revision History
03/05/2012 - Corrected link to version resolved AR.
02/14/2012 - Initial Release

NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 46273
创建日期 02/15/2012
Last Updated 12/15/2012
状态 Active
Type 综合文章
IP
  • AXI PCI Express (PCIe)