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AR# 46358

Vivado HLS - RTL Port and signal width implementation.

Description

Does the port width of my C code get optimized? How about the variables that are declared? Should I be concerned about mismatching assignments of RTL signal width warnings from RTL Synthesis tool?

解决方案

Top level port widthwill not be altered. Therefore, the correct sized type must be used.

The bit width of internal port between modulesmay be optimized.

It is possible that the RTL output may have a wider signal assigned to by a narrower signal. However, these warning can be safely ignored.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 46358
创建日期 02/15/2012
Last Updated 07/27/2012
状态 Active
Type 解决方案中心
Tools
  • AutoESL - 2010.b
  • AutoESL - 2011.1
  • AutoESL - 2011.3
  • More
  • AutoESL - 2011.4
  • Vivado - 2012.2
  • Less