We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 46375

Place & Route- DRC WARNING:PhysDesignRules:372 - Gated clock. Clock net length_​module/​length_​out is sourced by a combinatorial pin


I am receiving the warning below:

PhysDesignRules:372 - Gated clock. Clock net length_module/length_out is sourced by a combinatorial pin.


The warning is being issued because one of the clock net length_module/length_out is sourced by a combinatorial logic, making it a Gated-Clock.

Xilinx highly recommends that you use the CLB clock enable pin instead of gated clocks.

Gated clocks can cause glitches, increased clock delay, clock skew, and other undesirable effects.

Using clock enable saves clock resources, and can improve timing characteristic and analysis of the design.

Refer to page 60 of the user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/sim.pdf

If you are not finding any issues while generating the bitstream or board test, you can safely ignore this warning.

If you want to use CE instead, refer to the user guide mentioned above.
AR# 46375
日期 03/23/2015
状态 Active
Type 综合文章
  • ISE Design Suite