UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46747

Spartan-6 FPGA Design Assistant - Using block RAM CORE Generator and FIFO CORE Generator to setup the blocks for use in HDL code

Description

ThisAnswer Record provides information on how to setup block RAM or FIFOs with IP generated CORE Generator software.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.

解决方案

If you need to directly instantiate a block RAM or FIFO block into your design, the CORE Generator tool can be used. For more information on how to use the block RAM Generator or FIFO Generator IP cores, refer to the corresponding data sheets listed below for each IP core:

Once you generate either of these cores in the CORE Generator tool, the cores include an instantiation template (.veo file for verilog, .vho file for vhdl) that you can use to instantiate the core into your HDL code.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44744 Spartan-6 FPGA Solution Center N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
46740 Spartan-6 FPGA Design Assistant - Designing block RAM in Spartan-6 FPGAs N/A N/A
AR# 46747
创建日期 03/27/2012
Last Updated 12/15/2012
状态 Active
Type 综合文章
器件
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q