AR# 46752


Spartan-6 FPGA Design Assistant - Utilizing distributed memory in fabric


The contents of this answer record provide information on how distributed memory can be used to improve timing or reduce Block RAM utilization in your design.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.


Distributed memory is a memory element that is implemented using slice logic in fabric. In projects where available block RAM blocks are completely used up, distributed memory can be used to provide additional resources for implementing RAMs and ROMs.

In addition, in circumstances where timing is critical in your design, distributed memory can be used to help make it easier to meet timing in the design. Distributed memory is implemented in slice logic, so it has the added ability to be placed close to logic in areas where timing is critical.

The LogiCORE Distributed Memory Generator IP core can be used to implement memory elements based on distributed memory in your design. For more information on this core,see the LogiCORE IP Distributed Memory Generator v5.1 Data Sheet (DS322):



Answer Number 问答标题 问题版本 已解决问题的版本
44744 Spartan-6 FPGA Solution Center N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
46745 Spartan-6 FPGA Design Assistant - Designing configurable logic structures in Spartan-6 FPGAs N/A N/A
AR# 46752
日期 12/15/2012
状态 Active
Type 综合文章
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