AR# 47264


MIG 7 series DDR2/DDR3 - CAS Slot Usage - How it Relates to the PHY Control Word


In UG586 (PHY Only Section) states:

Memory commands and data can be sent directly through the PHY interface. Different command types are sent through different slots. The CAS Write Latency (CWL) command dictates the slot number to use for write/read commands. For an odd CWL value, CAS slot numbers 1 or 3 can be used; for an even CWL value, CAS slot numbers 0 or 2 can be used for the write/read commands.

Can the PHY support two data commands in a single phy control word (be it even odd, odd odd, or even even)?


The PHY cannot support two data commands in a clock cycle with four slots because each phy control word has a single field for data offset which is slot dependent. The use of a CAS slot can be seen in an example below with CWL = 5:

Cycle 0 1 2 3 4 5 6 78 9 10 11
cas_n 1 1 1 0 1 1 1 11 1 1 1
dq[0] x x x x x x x x v v v v

Valid data denoted as a "v" in dq line. When CWL is 5, that means it takes 5 cycles between the cas_n going low (asserted) and the valid data (dq). Each clock cycle will take a burst of four bits CAS and DQ, so the most efficient use case would be to have a valid data on all four bits. CAS slot is used to adjust where the CAS_N is shown, such that CAS_N slot number + CWL will result the start of valid data to always show on the first bit.

The MIG controller uses Slots 0 or 1 for data commands (dependent on even or odd CWL) and Slots 2 or 3 for non-data commands. It is possible, with a custom controller, to use Slots 2 or 3 for data commands so long as Slots 0 or 1 were not used for a data command within the same PHY Control Word.

Revision History:
4/13/2012 - Initial Release

AR# 47264
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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