AR# 47298


14.x PlanAhead - Known Issues for PlanAhead 14.x


This answer record lists the known issues for the PlanAhead tool in the ISE Design Suite 14.x releases.

Each known issue includes a link to another answer record that contains additional information on the issue.


Outstanding Known Issues in PlanAhead 14.7
(Xilinx Answer 34877) - PlanAhead cannot find floating PR license on a different server relative to the PlanAhead license location
(Xilinx Answer 36251) - PlanAhead incorrectly allows users to change the slew and drive attributes on inputs and export them to the ".ucf" file
(Xilinx Answer 38711) - In I/O planning project, the PlanAhead tool cannot create I/O ports for names with wildcard
(Xilinx Answer 41668) - DIFF_TERM is not supported as an I/O property for LVDS inputs
(Xilinx Answer 42010) - Multiple I/O properties cannot be set in one step
(Xilinx Answer 42152) - Some invalid MAP options for 7 series FPGAs are selectable (but not used)
(Xilinx Answer 42470) - Interactive DRC prevents correction of pin placement error in package view
(Xilinx Answer 42656) - Some Tcl 'help' commands result in an unexpected error
(Xilinx Answer 42700) - "More Colors" option cannot be used on Linux 64-bit
(Xilinx Answer 45458) - Resetting 3.4 MIG IP core in thePlanAhead tool deletes all core files
(Xilinx Answer 45468) - Referencing a pointer to a deleted port in Tcl, causes and Unexpected Error
(Xilinx Answer 46406) - Loading RTL issues inert "xlicmgr fails to read encrypted file: ERROR:sim:928" message for encrypted files
(Xilinx Answer 46718) - Multiple synthesis and implementation runs are not handled independently when adding Chipscope
(Xilinx Answer 47379) - IP Catalog does not add IP to project when directory contains Asian characters
(Xilinx Answer 47831) - Constraints are processed/applied by PlanAhead in a different format than with ISE command tools
(Xilinx Answer 50912) - MaxSkew timing violation is not highlighted red in Timing Checks display
(Xilinx Answer 51059) - SSN Report Noise Analysis Report is incorrectly shown as available for Spartan-6Q parts
(Xilinx Answer 52242) - PlanAhead - report_drc incorrectly reports GTL I/O incompatibility in Virtex-5 FPGA
(Xilinx Answer 53368) - PlanAhead - Constraining a differential pair with PULLUP and PULLDOWN ignores one of the constraints
(Xilinx Answer 55991) - Clock Interaction Report is not completely clear how it treats user TIG'ed paths as unconstrained
(Xilinx Answer 56268) - Intermittent crash while auto-placing all ports in a Virtex-5 pin planning project
(Xilinx Answer 56273) - Undo of drag-and-drop of a port in the Package View results in duplicate ports
(Xilinx Answer 57157) - Associate ELF file in the PlanAhead tool removes the DUT in simulation sources
(Xilinx Answer 57716) - Language Template typo for Mealy binary state machine
(Xilinx Answer 57873) - Differential pair assignment not recognized on Bank 7 (Site P77 and P78) for Spartan-3 3400-tw144

Known Issues Resolved in PlanAhead 14.7


Known Issues Resolved in PlanAhead 14.6
(Xilinx Answer 53874) - The value of the More Options field under Bitstream Settings is not being saved
(Xilinx Answer 55410) - launch_xpa failes with "ERROR: [Common 17-180] Spawn failed: No error..."

Known Issues Resolved in PlanAhead 14.5
(Xilinx Answer 52786) - 14.4 PlanAhead - SSN reporter does not analyze I2C IOSTANDARD pins and reports Partial Analysis:Passed
(Xilinx Answer 53809) - When creating a project for the ZC706 Evaluation Kit in PlanAhead 14.4, the corresponding part is incorrect
(Xilinx Answer 53831) - PlanAhead changes not saved in UCF file when multiple instances are "Fixed" at once
(Xilinx Answer 53867) - PlanAhead hangs when the changes are made to the test bench in an external editor and isim is relaunched
(Xilinx Answer 54059) - The PlanAhead tool is hanging after running ISim and re-launching the simulation through the ISim GUI
(Xilinx Answer 54856) - Importing an ISE project containing many IP cores can lead to problems when regenerating the IP

Known Issues Resolved in PlanAhead 14.4
(Xilinx Answer 51519) - A differential LVDS pair reports incorrectly P-side as input and N-side as output in PAD report
(Xilinx Answer 52753) - Launching an IP customization GUI from the IP Catalog takes several seconds
(Xilinx Answer 55842) - "ERROR:MapHelpers:151 - Error while processing the area group range."
(Xilinx Answer 55872) - The small item count bins are very difficult to select in the Histogram View

Known Issues Resolved in PlanAhead 14.3
(Xilinx Answer 45651) - PlanAhead has no ability to copy an IP core to create a slight variation?
(Xilinx Answer 46406) - Incorrect message issued for encrypted file that cannot be viewed
(Xilinx Answer 51309) - Saving I/O Pin Planning project to a new UCF file results in java.lang.NullPointerException
(Xilinx Answer 51574) - ERROR: [Common 17-161] Invalid option value specified for 'objects'
(Xilinx Answer 51888) - The DIFF_HSTL_II_DCI_18 I/O standard is not supported for bankType Dedicated in bank I/O Bank: 4 (Dedicated)
(Xilinx Answer 52496) - INTERNAL EXCEPTION produced when "Implementation Settings" try to be accessed from the Design Flow pane
(Xilinx Answer 52984) - Device View for Hi-rel Parts is shown with Overlapping I/O
(Xilinx Answer 52985) - Report Utilization button is shown for Elaborated design
(Xilinx Answer 53725) - ERROR: [Common 17-39] 'launch_isim' failed due to earlier errors

Known Issues Resolved in PlanAhead 14.2
(Xilinx Answer 38656) - PlanAhead is not able to infer a differential pair based on signal names
(Xilinx Answer 45475) - PlanAhead is unable to import ISE IP cores if they are not the latest version of the IP
(Xilinx Answer 47398) - Re-running Synthesis on XPS design fails to regenerate / find xps sub modules
(Xilinx Answer 50159) - Using ModelSim from the PlanAhead GUI produces "ERROR:[Runs-112] Failed to locate the ModelSim 'vsim" executable program
(Xilinx Answer 50262) - Implementing an EDK project results in: ERROR:NgdBuild:634 - Cannot open input BMM file
(Xilinx Answer 51003) - The PlanAhead Schematic viewer of does not group unsigned-vectors array elements as a bus
(Xilinx Answer 55733) - Language option is not set for simulation and synthesis targets in the PlanAhead utility scripts when XPS project is imported
(Xilinx Answer 55755) - 14.1 PlanAhead - Archive Project with -force option gives : ERROR: [Common-70] Application Exception: project already exists with this alias
(Xilinx Answer 55852) - If I import an ISE project, the PlanAhead tool creates .ppr and project in the ISE project directory
(Xilinx Answer 55878) - Critical Error message of "Create run with incorrect top" should not have an "Ignore" checkbox

AR# 47298
日期 11/11/2013
状态 Archive
Type 已知问题
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