This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v10.6 Core released in ISE Design Suite 14.1), and contains the following information:
- New Features
- Supported Devices
- Resolved Issues
- General Information
- Known Issues
For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at:
- ISE 14.1 software support
- Virtex-4, Virtex-5, Virtex-6, and Virtex-6L FPGA
- (Xilinx Answer 42573) - SPI-4.2: Timing errors seen when performance is 1.2 Gb/s and the TSClk is on global clocking.
- Spartan-6 FPGA support has been removed in ISE 12.4 onwards
Description: Users cannot target Spartan-6 devices when using the SPI-4.2 core.
Workaround: Use an alternative device like Virtex-6 CXT. (Xilinx Answer 39106)