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AR# 47628

7 Series Integrated Block for PCI Express v1.4 (ISE 14.1 / Vivado 2012.1) - Timing violations in certain IP configurations

描述

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

There are certain IP configurations that do not meet timing.

解决方案

This is a known issue and will be fixed in a future release of the core. If you run intotiming violations with theimplementation of the default core generation, please create aWebCase with Xilinx Technical Supportand submit the XCO file and the timing report.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

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主要问答记录

AR# 47628
日期 05/20/2012
状态 Active
Type 已知问题
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