This Release Note and Known Issues Answer Record is for the AXI Interconnect and contains the following information:
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025).
|(HDL) Synchronous clock-domain crossings are performed completely within the clock converter module, so multi-cycle clock constraints are no longer necessary and are no longer generated. ACLK period parameter is used only for async clock conversions, and the async CDC clock constraints will still succeed using a TIG, even if the ACLK period is not specified.||1.06.a|
|(HDL) Asynchronous clock-domain crossings are now performed using a single instance of 5-channel AXI FIFO (per interface slot) instead of 5 separate calls to fifo_generator, thereby decreasing compilation time. Timing constraints for async CDC are now conditionally generated only if the interconnect instance performs any async conversions.||1.06.a|
|(Tcl) Added Optimization Alerts for conditions including C_INTERCONNECT_DATA_WIDTH narrower than widest MI or different than all SI/MI slots, C_INTERCONNECT_ACLK_RATIO slower than fastest MI or different than all SI/MI slots, redundant 32-deep FIFO with async clock-conv, Type-1 reg-slice on AW/AR/B channel or AXI4-Lite slot, SAMD crossbar with all AXI4-Lite masters/slaves.||1.06.a|
|Initial release of v1.06.||1.06.a|
|Setting parameter C_S_AXI_IS_INTERCONNECT = 1 is not yet supported.||1.06.a|
|The diagnostic control interface (S_AXI_CTRL) is not implemented. The parameter C_USE_CTRL_PORT is therefore forced to 0.||1.06.a|
This table correlates the core version to the first ISE software release version in which it was included.
|Core Version||ISE Software Version|