coregen -p coregen.cgp -b mig_7series_v1_4.xco
When regenerating a core in MIG 7 series, verify that the input clock period setting has not changed.
This would effect the CLKIN_PERIOD and PLL mult/divide parameters in the top level RTL, input clock period constraint in the UCF, and the input clock period settings in the mig.prj and datasheet.txt files.
To work around this issue, manually change these settings back to the original settings.
This issue is resolved in MIG 7 series v1.6 available with ISE Design Suite 14.2.
| AR# 47699 | |
|---|---|
| 日期 | 08/21/2014 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| IP | |