解决方案
The following example shows how the power-up sequence of the memory specification and Xilinx's MIG QDRII+ controller differ:
QDRII+ memory power-up sequence (Cypress and Samsung memory specifications):
1. Apply power and keep DOFF# at Low state.
2. Just after the stable power and clock(K,K), take DOFF# to High.
3. Provide stable DOFF# (high), power and clock (K, K) for 20 microseconds (Cypress)/ 2048 clock cycles (Samsung) to lock the PLL.
Power-up sequence that MIG Virtex-6 QDRII+ follows:
1. Apply power and keep DOFF# at Low state.
2. After the stable power and clock(K,K), wait for 200 microseconds and then take DOFF# to High.
3. Provide stable DOFF# (high), power and clock (K, K) for 2048 clock cycles (Samsung & Cypress) to lock the PLL.
There are two issues resulting from this difference:
- 200 microseconds requirement after the MIG PLL lock is unnecessary and can be removed.
- MIG Virtex-6 FPGA QDRII+ IP uses 2048 clocks to stabilize the PLL, but it is valid only for Samsung.
As a result, an update for Cypress parts is needed to wait for 20 microseconds regardless of the clock period.
To work around this issue:
- Increase the CLK_STABLE parameter to equal 20 microseconds depending on the frequency the QDR memory is running at.
You can find CLK_STABLE in the example top module, or use the design top module and change it to CLK_STABLE = (20*1000*1000/(CLK_PERIOD)).
- Skip the 200 us delay by changing the following local parameter to zero.
Find INIT_DONE in phy_read_sync.v/vhd and change the value as below:
Old value:
localparam INIT_DONE = (SIM_INIT_OPTION != "NONE") ? 10 : (200*1000*1000/CLK_PERIOD);
New value:
localparam INIT_DONE = 0;
Note: The second workaround for INIT_DONE is optional.
It will not cause functional problems.
It will increase initialization time.