AR# 47773


MIG 7 Series DDR3 RDIMM - Designs are not working in hardware


Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

All MIG 7 series DDR3 RDIMM designs will fail in hardware during the DQS Found Stage of calibration (pi_dqs_found_error=1) as a result of the MRS programming sequence being handled incorrectly. 

This is due to the chip select logic always holding chip select (cs_n) Low, causing calibration to continuously program MRS registers which corrupts the MRS sequencing.


The chip select (cs_n) signal needs to be active each time a valid command is available at the interface.

Please open a WebCase with Xilinx Technical Support for a work-around.
AR# 47773
日期 08/14/2014
状态 Active
Type 已知问题
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