AR# 50183


Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1/Vivado 2012.1) - User Clock Frequency is Fixed and not Selectable in the Core Configuration GUI


Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The Virtex-7 FPGA Gen3 Integrated Block for PCI Express product guide contains a table, "Data Width and Clock Frequency Settings for the Client Interfaces," 

It mentions that different user clock frequencies are supported for the same speed, link width, and AXI-4 stream interface width. 

However, in the core configuration GUI, this frequency is not selectable and is fixed to a constant value.

How can I change the frequency to a different supported frequency other than the one in the GUI?


The Core Configuration GUI does not support all of the available configurations. 

However, if you require a different frequency listed in the product guide, you can edit the xilinx_pcie_3_0_7vx_ep.v and xilinx_pcie_3_0_7vx_rp.v source files as per requirement. 

Both of these files are generated with the generation of the core. 


The following parameter default values need to be changed in the above files.

If you are generating the core in Vivado 2012.1, you will need to make the modification in the pcie3_7x_v1_1_0.v file as well. 

This file is located in the 'sim' and 'synth' directories.

parameter integer USER_CLK2_FREQ = <IF_FREQ>

Where IF_FREQ can take one of the following three values:

2 - 62.5MHz
3 - 125MHz
4 - 250MHz

The above information is not currently in the product guide. 

This information will be included in the product guide in the next release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
06/06/2012 - Initial release

AR# 50183
日期 03/16/2015
状态 Active
Type 已知问题
People Also Viewed