If you are using the Tri-Mode Ethernet MAC v5.3 example design generated in VHDL for a 1G only RGMII interface, errors occur during Synthesis.
The issue only occurs for this configuration.
The following errors are seen:
Parsing architecture <PHY_IF> of entity <tri_mode_eth_mac_v5_3_rgmii_v2_0_if>.
ERROR:HDLCompiler:1314 - "C:\designs\coregen\z7\tri_mode_eth_mac_v5_3\example_design\physical\tri_mode_eth_mac_v5_3_rgmii_v2_0_if.vhd" Line 349: Formal port/generic <i> is not declared in <bufgmux>
ERROR:HDLCompiler:854 - "C:\designs\coregen\z7\tri_mode_eth_mac_v5_3\example_design\physical\tri_mode_eth_mac_v5_3_rgmii_v2_0_if.vhd" Line 123: Unit <phy_if> ignored due to previous errors.
VHDL file C:\designs\coregen\z7\tri_mode_eth_mac_v5_3\example_design\physical\tri_mode_eth_mac_v5_3_rgmii_v2_0_if.vhd ignored due to error
A BUFGMUX is instantiated when a BUFG should be used.
To fix this, change the following in the core_name_rgmii_v2_0_if.vhd file:
bufg_gmii_rx_clk : BUFGMUX
port map (
I => rx_clk0,
O => rx_clk_int
);
To:
bufg_gmii_rx_clk : BUFG
port map (
I => rx_clk0,
O => rx_clk_int
);
AR# 50321 | |
---|---|
日期 | 11/06/2014 |
状态 | Active |
Type | 综合文章 |
IP |