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Implementation Details | |||
---|---|---|---|
Design Type | PS and PL | ||
SW Type | Standalone | ||
CPUs | Single CPU | ||
PS Features | GIC, UART1 | ||
PL Cores | AXI TIMER | ||
Boards/Tools | ZC702 | ||
Xilinx Tools Version | Vivado 2014.4 or 2016.1 | ||
Other details | USB cable II or Digilent cable, mini cable, PS configuration is ZC702 template. | ||
Address Map | |||
Base Address | Size | Bus Interface | |
AXI TIMER | 0x42800000 | 64K | S_AXI |
Step by Step Instructions:
Note: Be careful of the interrupt ID number.
In this design ID 61 was defined in xparameters.h.
ID mapping is different in Vivado 2013.x and Vivado 2014.x or later, See (Xilinx Answer 62107) for more details.
Expected Results:
Interrupt information will print in the terminal repeatedly.文件名 | 文件大小 | File Type |
---|---|---|
Pl_timer_intr_test.c | 4 KB | C |
zynq_design_bd_2014_4.tcl | 8 KB | TCL |
zynq_design_bd_2016_1.tcl | 69 KB | TCL |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
51779 | Zynq-7000 SoC - Example Designs and Tech Tips | N/A | N/A |
AR# 50572 | |
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日期 | 05/18/2018 |
状态 | Active |
Type | 综合文章 |
器件 | |
Tools | |
Boards & Kits |