AR# 50572
Zynq-7000 Example Design - Interrupt handling of PL generated interrupt
描述
This example design implements a timer in PL, and the interrupt of the timer will ring the CPU by GIC IRQ.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.
A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It is up to the user to "update" these tips for future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.
Limited support is provided by Xilinx on these Example Designs.
A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It is up to the user to "update" these tips for future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.
Limited support is provided by Xilinx on these Example Designs.
解决方案
| Implementation Details | |||
|---|---|---|---|
| Design Type | PS and PL | ||
| SW Type | Standalone | ||
| CPUs | Single CPU | ||
| PS Features | GIC, UART1 | ||
| PL Cores | AXI TIMER | ||
| Boards/Tools | ZC702 | ||
| Xilinx Tools Version | Vivado 2014.4 or 2016.1 | ||
| Other details | USB cable II or Digilent cable, mini cable, PS configuration is ZC702 template. | ||
| Address Map | |||
| Base Address | Size | Bus Interface | |
| AXI TIMER | 0x42800000 | 64K | S_AXI |
Step by Step Instructions:
- Open Vivado 2014.4 or 2016.1
- Enter the following command in the Vivado Tcl console:
cd {<full directory of zynq_design_bd.tcl >} - Enter the following command in the Vivado Tcl console:
source zynq_design_bd_2014_4.tcl" or "source zynq_design_bd_2016_1.tcl" - After block design creation has completed, generate the output products for the block design.
- After the product is generated, generate the wrapper.
- Generate the bitstream.
- After the bitstream is generated, open the implemented design.
- In the File menu, click Export Hardware for SDK, and check all selections.
- After SDK has launched, create the BSP and an empty application.
- Import C code to the empty application project.
- Set up the terminal to watch UART output.
- Run the application.
Note: Be careful of the interrupt ID number.
In this design ID 61 was defined in xparameters.h.
ID mapping is different in Vivado 2013.x and Vivado 2014.x or later, See (Xilinx Answer 62107) for more details.
Expected Results:
Interrupt information will print in the terminal repeatedly.
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附件
| 文件名 | 文件大小 | File Type |
|---|---|---|
| Pl_timer_intr_test.c | 4 KB | C |
| zynq_design_bd_2014_4.tcl | 8 KB | TCL |
| zynq_design_bd_2016_1.tcl | 69 KB | TCL |
链接问答记录
主要问答记录
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 51779 | Zynq-7000 SoC - Example Designs and Tech Tips | N/A | N/A |
| AR# 50572 | |
|---|---|
| 日期 | 05/18/2018 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| Tools | |
| Boards & Kits | |