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For Verilog Design:
1. Open the ISIM Properties window by Right Clicking on "Simulate Behavioral Model".
2. Use the switch -timescale and set the resolution accordingly in Other Compiler Options. For example "-timescale 1ps/1fs"
Syntax:
For VHDL Design:
1. Open the ISIM Properties window by Right Clicking on Simulate Behavioral Model.
-timeprecision_vhdl<time_precision>
This specifies the time precision (unit of accuracy) for all VHDL design units.
The time_precision is entered as a number (1|10|100|...) followed by the unit (fs|ps|ns|us|ms|s).
AR# 50577 | |
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日期 | 07/28/2014 |
状态 | Active |
Type | 综合文章 |
器件 |
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