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MIG 7 Series DDR3/DDR2 - Some configurations fail to meet timing due to logic not being placed properly
Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 45195).
In some MIG 7 series DDR3/DDR2 configurations, some logic is not being placed within the correct clock region.
This causes excessive net delay going to some of the hard blocks (for example OUT_FIFO).
This is an issue related to the placement algorithm and not to the MIG design itself.
To work around the issue, the user can manually set AREA_GROUP constraints to force the placer to place the logic within the same clock region, or the following environment variable can be set:
For instructions on how to set up an environment variable please refer to (Xilinx Answer 11630).