In some MIG 7 series DDR3/DDR2 configurations, some logic is not being placed within the correct clock region.
This causes excessive net delay going to some of the hard blocks (for example OUT_FIFO).
For instructions on how to set up an environment variable please refer to (Xilinx Answer 11630).
AR# 50698 | |
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日期 | 08/13/2014 |
状态 | Active |
Type | 已知问题 |
器件 | |
IP |