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AR# 50890

7 Series FPGAs Transceivers Wizard Flow in Vivado Design Suite 2012.2/2012.3/2012.4


This answer record describes the steps to follow to use the 7 series FPGAs Transceivers Wizard in the Vivado 2012.2/2012.3/2012.4 tools.


There aredifferent versions of the 7 series FPGA Transceiver Wizard available in Vivado Design Suite 2012.2,2012.3 and 2012.4 toolsto support the different silicon versions of 7 Series FPGA transceivers. For details, refer to(Xilinx Answer 46048).

To generate or implement the core, follow these steps:

1. Invoke the CORE Generator tool and generate the correct 7 series FPGA Transceivers Wizard versionfiles (based on the silicon version as mentioned above).

2. Run the vivado_rdn.sh/bat file from the command prompt, make sure LD_LIBRARY_PATH is set properly.

3. To run the implementation in GUI mode:

  • Open the Vivado tool in GUI mode and then create a project.
  • From the "Sources" window, click on the "Add Sources (Alt + A)" button which will open "Add Sources" window.
  • Alternatively the "Add Copy of Source" can be used, the benefit of this is that the original files will not be modified and can be retained as a golden example if any changes are made.
  • From the "Add sources" or "Add Copy of Source" window, add wizard generated source files, netlist(.ngc) files and constraint files(.xdc) to the project.
  • If adding source files into project through "Add Sources" window make sure "Copy Sources into Project" check-box is unchecked before clicking the "Finish" button. Without this un-check option the synthesis tool will not able to read BRAM-initialized dat files.

4. After all the above GUI mode steps are completed successfully, any of the implementation flow options can be run from the Vivado GUI.

5. When running implementation in GUI mode: to avoid DRC errors due to unconstrained pins in the design, please use the following command in the TCL console:

set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]

Note: For more information on MYXILINX and LD_LIBRARY_PATH environment variables, see (Xilinx Answer 2493).

To run the transceiver wizard simulation using Vivado integrated Modelsim/Questa/XSIM (Launch sim), follow these steps:

1. Copy ".dat" files to sim directory using "Add Sources -> Add or Create Simulation Sources tab in GUI.

2.Copy all designand testbench files (all .v or .vhd) using "Add sources -> Add or Create Design Sources tab in GUI.

3. For Modelsim/Questa, point to the correct compiled library location by selecting 'Simulation settings' and setting the path at 'Compiled library location' tab. (for example,it can be set to /proj/xbuilds/clibs/ids_14.3_P.40xd.1.0/modelsim/10.1a/lin64/lib).

4. Set the top module name by clicking on 'Simulation top module name'.

5. Run Simulation.

TCL commands to add dat files to simulation directory.
add_files -fileset sim_1 -norecurse {project_1/project_1.srcs/sources_1/ip/gtwizard_v2_3_0/gtwizard_v2_3_0/simulation/functional/gt_rom_init_rx.dat project_1/project_1.srcs/sources_1/ip/gtwizard_v2_2_0/gtwizard_v2_2_0/simulation/functional/gt_rom_init_tx.dat}



Answer Number 问答标题 问题版本 已解决问题的版本
41613 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List N/A N/A
AR# 50890
日期 12/10/2012
状态 Active
Type 综合文章
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado - 2012.2
  • Vivado - 2012.3
  • Vivado - 2012.4
  • 7 Series FPGAs Transceivers Wizard