This Answer Record covers Known Issues with v2.2 of the 7 Series FPGAs Transceivers Wizard targeting GTZ Transceivers in Vivado Design Suite 2012.2.
In order to successfully use the 7 Series Transceiver Wizard output in Vivado 2012.2, you must:
create_clock -name rxusrclk1 -period 6.206 rxusrclk1
create_clock -name txusrclk0 -period 6.206 txusrclk0
create_clock -name TXOUTCLK0 -period 6.206 [get_pins -hierarchical *gtze2_octal_north/TXOUTCLK0]
create_generated_clock -name TXUSRCLK0 -divide_by 1 -source [get_pins -hierarchical *gtze2_octal_north/TXOUTCLK0] [get_pins -hierarchical -filter {name=~*gtze2_inf_north*clkbuflbtx0*CLKOUT}]
create_clock -name RXOUTCLK0 -period 6.206 [get_pins -hierarchical *gtze2_octal_north/RXOUTCLK0];
create_clock -name DRPCLK_IN -period 20 [get_ports DRPCLK_IN]
文件名 | 文件大小 | File Type |
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beachfront_placeNroute.tcl | 101 KB | TCL |
AR# 51016 | |
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日期 | 01/16/2015 |
状态 | Active |
Type | 已知问题 |
器件 | |
Tools | |
IP |