I have imported my ISE project into PlanAhead, but when I run Synthesis, there is a module re-declaration error for one of the IP cores in the design.
For Example:
[HDLCompiler 687] Illegal redeclaration of module <RAM_core>. ["//EDA/project_1/project_1.srcs/sources_1/ip/RAM_core/RAM_core_synth.v":47]
This issue might be due to having both a <core_name>_synth.v and a <core_name>.v in the synthesis folder of the core.
To resolve the issue, follow the steps below:
AR# 51066 | |
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日期 | 06/18/2018 |
状态 | Active |
Type | 综合文章 |
Tools |