描述

I have imported my ISE project into PlanAhead, but when I run Synthesis, there is a module re-declaration error for one of the IP cores in the design.

For Example:

[HDLCompiler 687] Illegal redeclaration of module <RAM_core>. ["//EDA/project_1/project_1.srcs/sources_1/ip/RAM_core/RAM_core_synth.v":47]

解决方案

This issue might be due to having both a <core_name>_synth.v and a <core_name>.v in the synthesis folder of the core.

To resolve the issue, follow the steps below:

1. Right click on the IP core and select Reset
2. Right Click on the IP core again and select Generate, then Select the Synthesis box for generation.