Version Found: 1.5
The data rates specified in MIG 7 Series for DDR3L components targeting Virtex-7/Kintex-7 -2 speed grade FPGAs are slower than the data rates specified in the DC and Switching Characteristics data sheets (DS183/DS182). Can the higher data rates specified in the data sheets be achieved and how?
The data rates specified in the DC and Switching Characteristics are correct and supported by Xilinx. The values specified in MIG are incorrect and will be updated in MIG 1.7 to be released in ISE 14.3/Vivado 2012.3 design suites.
To generate a MIG design targeted at the higher DC and Switching Characteristics data sheets, select an equivalent 1.5V DDR3 device within MIG, generate the desired design, and then change the I/O standards to 1.35V SSTL in the generated UCF.