Description

I am trying to implement a Kintex-7 design but am receiving an error during implementation:

ERROR:Place:1388 - Unroutable Placement! A BUFDS / GT clock component pair have
   been found that are not placed at a routable BUFDS / GT site pair. The BUFDS
   component
   <i_jesd204_rx_block/i_gtwizard_v1_5_rx2_top/gt_usrclk_source/ibufds_instQ0_CL
   K1> is placed at site <IBUFDS_GTE2_X0Y5>. The GT component
   <i_jesd204_rx_block/i_gtwizard_v1_5_rx2_top/gtwizard_v1_5_rx2_i/gt0_gtwizard_
   v1_5_rx2_i/gtxe2_i> is placed at site <GTXE2_CHANNEL_X0Y8>. The GT is driven
   by this BUFDS in regular mode and they must be placed in the same clock
   region to be routable because the BUFDS connects to the GT on a GTREFCLK pin.
   Furthermore, depending on the GTREFCLK bit used, only some BUFDS sites in the
   same clock region are routable to it. Check usage documents for routability
   of the device. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN
   "i_jesd204_rx_block/i_gtwizard_v1_5_rx2_top/gt_usrclk_source/ibufds_instQ0_CL
   K1.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "i_jesd204_rx_block/i_gtwizard_v1_5_rx2_top/gtwizard_v1_5_rx2_i/gt0_gtwizard_
   v1_5_rx2_i/gtxe2_i.GTREFCLK0" CLOCK_DEDICATED_ROUTE = FALSE; >

解决方案

In a Kintex-7 device, you can have 2 reference clocks for the GTXE2_CHANNEL component. 

This needs to be driven by an IBUFDS_GTE2 component in the device.

In 7 series devices these IBUFDS_GTE2 components are arranged in pairs.

Only one pair can drive refclk0 on the GTXE2_CHANNEL and the other pair drives the refclk1 on the GTXE2_CHANNEL.

In the example generating the error,  the IBUFDS_GTE2 refclk1 pair have been loc'd down to drive the refclk0 on the GTXE2_CHANNEL. 

This is not routable and as a result the error is generated.

The work-around is to reverse the LOC constraints.