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AR# 51533

Design Assistant for Vivado Synthesis - Help with SystemVerilog Tasks and Functions Support

描述

This answer record describes SystemVerilog tasks and functions supported by Vivado Synthesis and also provides coding examples for them. These coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example.

解决方案

SystemVerilog Tasks and Functions that are supported in Vivado Synthesis.

The following are the SystemVerilog Tasks and Functions structures that are supported in Vivado Synthesis. Please refer to Table 1-1 in this answer record for the related coding examples.

  1. SystemVerilog has static and automatic tasks and functions. Vivado synthesis treats all tasks and functions as automatic.
  2. For non-void functions, a value can be returned by assigning the function name to a value or by using return with a value. The return statement shall override any value assigned to the function name.

 

Coding example for Tasks and Functions

Table 1-1
Coding example name Data Types
task_function_example1.zip

 

  • automatic function and void function
  • task

附件

文件名 文件大小 File Type
task_function_example.zip 2 KB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
51360 Design Assistant for Vivado Synthesis - Help with SystemVerilog Support N/A N/A
AR# 51533
日期 04/03/2013
状态 Active
Type 解决方案中心
Tools
  • Vivado Design Suite
的页面