AR# 51616

Zynq-7000 Example Design - GMII Ethernet through EMIOs

描述

The example design routes the EMIO GMII interface to FPGA I/Os to be used by an FMC card with an Ethernet PHY.An Inreviun TDS-FMCL-PoE card is used for this example.An alternate board can be the Inrevium FMCL-GLAN card.Note that the FMC pinout is different for each board.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs. Xilinx 对这些范例设计仅提供有限的支持。

实现详情
PS 和 PL

Standalone with LwIP.

Linux has been tested as well.Linux would require a patch to set the PHY interface to GMII.Linux by default sets the external PHY to RGMII.

单个 CPU
DDR, ETH0
Custom GMII synchronization pcore
ZC702, FMCL-PoE
EDK 14.2
--
基址大小总线接口
0x412000004KS_AXI
Files Provided
Capture.JPG


 

解决方案

 
Only 1000 Mbps mode is supported.There is no speed detection.The ZC702 200 MHz system clock is used to generate the 125 MHz GTX clock for the Ethernet core and the PHY on the FMC.
The custom pcore is based on the CORE Generator Ethernet GMII wrapper.A PLL is used to deskew the RX Clock.


Step by Step Instructions

1.       Open the xmp file with XPS
2.       Generate the bitstream
3.       Export the design to SDK
4.       Open SDK, create a new workspace
5.       Create a new C application based on the echo server template
6.       Connect the FMCL-PoE board to FMC2 of the ZC702.J12 should be populated.
7.       Connect the JTAG, UART, and Ethernet cables
5.       Power-on the ZC702 board
9.       Run the echo server application from SDK


 
 

附件

文件名 文件大小 File Type
ZC702_Eth_EMIO_GMII_142.zip 131 KB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
51779 Zynq-7000 SoC - Example Designs and Tech Tips N/A N/A
AR# 51616
日期 06/08/2020
状态 活跃
Type 一般类
器件
Tools
Boards & Kits