The example design routes the EMIO GMII interface to FPGA I/Os to be used by an FMC card with an Ethernet PHY. An Inreviun TDS-FMCL-PoE card is used for this example. An alternate board can be the Inrevium FMCL-GLAN card. Note that the FMC pinout is different for each board.
Note: An Example Design is an answer record that providestechnical tips to test a specific functionalityon Zynq-7000.Atip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. It isup to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design tofulfill his needs. Limited support is provided by Xilinx on these Example Designs.
|Design Type||PS and PL|
Standalone with LwIP.
Linux has been tested as well. Linux would require a patch to set the PHY interface to GMII. Linux by default sets the external PHY to RGMII.
|PS Features||DDR, ETH0|
|PL Cores||Custom GMII synchronization pcore|
|Xilinx Tools Version||EDK 14.2|
|Base Address||Size||Bus Interface|
Archived XPS project with custom pcore.
Step by Step Instructions
|Boards & Kits||