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AR# 51878

Zynq-7000 Debug - Routing PJTAG to the Mictor connector on FMC-105 attached on ZC702

描述

This example design uses the FMC1 connector on the ZC702 board to attach the XILINX HW_FMC-105-DEBUG board. 

The TRACE port gets routed via EMIO to the Mictor connector on the FMC-105. 

Also, the PJTAG is routed via EMIO on J16 to the mezzanine board and then wired to J19.

The result is that a debugger (for example Lauterbach) can use the JTAG connection available on the Mictor connector.

解决方案

Implementation Details

  • Design Type:         PS & FPGA
  • SW Type:              Standalone
  • PS Features:         TRACE
  • PL Cores:               ---
  • Boards/Tools:        ZC702
  • SW Tools/Version: EDK 14.7 / Vivado 2014.1


Files Provided

  1. Archived XPS 14.7 project
  2. Tcl file for IPI design, HDL wrapper file and constraint files


 

Note: A version of the design built using Vivado IP Integrator is also attached.

  1. Create a new Vivado project targeting the ZC702.
  2. Source the .tcl to create the block design.
  3. Add the constraints files.
  4. Generate the output products.
  5. Add the HDL wrapper and generate the bitstream.

Note:

  1. A work-around for a EMIO TPIU boot issue on 2014.1 is added, for more detail of this issue, please see (Xilinx Answer 60755)
  2. The work-around suggested for (Xilinx Answer 60066) is added to HDL wrapper in Vivado project.


Note: The Lauterbach POD checks if power is present on PIN 14 of the Mictor connector.

The FMC-105 card has PIN 14 not connected.

Shorting together PIN 12 and 14 on the FMC-105 is necessary to connect PIN 14 to VADJ and PASS the Lauterbach check of the power.

Steps to set up the XPS project:

1) Set up the connection on the board as shown in the attached picture.

TCK => J16-6 => FMC1_LA30_P => E21 on the Zynq BANK.
TMS => J16-8 => FMC1_LA30_N => D21 on the Zynq BANK.
TDI => J16-10 => FMC1_LA31_P => A16 on the Zynq BANK.
TDO => J16-12 => FMC1_LA31_N => A17 on the Zynq BANK.

2) Generate a bitstream from the attached XPS project ( Note PJTAG routing in system.ucf).

3) Build a BOOT.bin containing the FSBL + system.bit + u-boot

4) Copy your BOOT.bin on to the SD card

5) Boot from the SD card and Independent JTAG.

6) On the Terminal wait for the u-boot prompt and stop autoboot (At this time level shifters are enabled).

7) Connect your debugger to the PJTAG and TRACE port via the Mictor connector.

Steps to set up the Vivado project:

  1. Create a blank Vivado project targeting the ZC702 board.
  2. Type the following command in the Vivado Tcl console.
    cd {<full directory of ipi_design_20141.tcl >}
  3. Type the following command in the Vivado Tcl console:
    source mictor_ipi_14_1.tcl
  4. After block design creation has completed, generate the output products for the block design.
  5. After the product is generated, add the attached design_1_wrapper.v. This is a work-around for (Xilinx Answer 60066)
  6. Add the constraint files .xdc to the Vivado project.
  7. Generate the bitstream.
  8. After the bitstream is generated, open the implemented design.
  9. In the File menu, click Export Hardware for SDK, and check all selections.
  10. After SDK has launched, create the FSBL and BSP.
  11. Open ps7_init.c in the FSBL, and comment every line of EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x80000000U),.
  12. Save ps7_init.c, and compile the FSBL again.
  13. Create a hello world application.
  14. We can generate BOOT.bin with the generated ELF files of the FSBL and a hello world together with the bitstream.


Note: Normally steps 11 and 12 are not needed if the PL is programed before running ps7_init.

Setup Picture:


附件

文件名 文件大小 File Type
zc702mictor_2014_1.zip 6 KB ZIP
zc702_mictor_14_7.zip 1 MB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
50863 Zynq-7000 AP SoC - 调试 N/A N/A
AR# 51878
日期 11/08/2017
状态 Active
Type 综合文章
器件
  • Zynq-7000
Tools
  • ISE Design Suite - 14.7
  • Vivado Design Suite - 2014.1
Boards & Kits
  • Zynq-7000 SoC ZC702 Evaluation Kit
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