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AR# 52095

Zynq-7000 Debug - 2014.1 Setup the TRACE port via EMIO and PJTAG via MIO PMOD on the ZED board


This example design shows how to connect the TRACE port on a Zynq-7000 device via EMIO to the mictor on the XILINX HW-FMC-105-DEBUG board attached to the FMC connector of the ZED board.

It also routes the PJTAG to the MIO PMOD on the ZED board. In this way, it is possible to debug the PL (using XILINX tools) and the PS (using third-party tools) independently, using the AVNET PMOD-7ZJTAG adapter.


In the design:

  • In the Zynq TAB, PJTAG is routed to MIO 10 .. 13.
  • FCLK_CLK0 is used to feed the EMIO port EMIOTRACECLK and a divided by two version of FCLK_CLK0 is used to feed the external port TRACECLK_pin. This is because ARM defines two separate clocks, TRACECLKIN and TRACECLK, where TRACECLK = TRACECLKIN/2. TRACECLKIN is the input clock to the CoreSight components, and TRACECLK is the output clock that goes to the Lauterbach debugger. On EMIO, the EMIOTRACECLK port is actually TRACECLKIN. You will need to generate your own divide-by-2 version of this clock in the PL, and output it to the TRACECLK_pin.
  • The ucf constrains for the TRACE port needs to match the ZED board layout

Step-by-step instructions:

  1. Connect the XILINX HW-FMC-105-DEBUG board to the FMC connector on the ZED board
  2. Connect your TRACEr to the mictor connector on the XILINX HW-FMC-105-DEBUG board
  3. Connect the AVNET PMOD-7ZJTAG adapter to the MIO PMOD connector on the ZED board
  4. Connect your 20-pin DEBUG header to the 20-pin connector on the AVNET PMOD-7ZJTAG adapter
  5. Setup the boot mode jumpers to boot from SD card in Independent JTAG mode.
  6. Create a BOOT.bin ( to copy on your SD card ) that contains:
    • the FSBL created from the attached SDK project
    • the bitstream created from the attached XPS project
    • the "Hello World" example created from the SDK project
  7. Boot from SD card and wait until the DONE LED lights up and "Hello World" prints on the terminal ( 115200, 8, 1, N, N )

Steps to set up the Vivado project:
1.     Create a blank vivado project targeting the ZED board.
2.     Type cd {<full directory of ar52095_bd_tcl.tcl>} in the Vivado tcl console.
3.     Type source ar52095_bd_tcl.tcl in the tcl console.
4.     After block design creation has completed, generate the output products for the block design.
5.     After the product is generated, create the top HDL for the block design, and modify the width of TRACE_DATA to 16 like output [15:0]TRACE_DATA; wire [15:0]TRACE_DATA;.
6.     Add the constraint file system.xdc to the Vivado project.
7.     Generate the bitstream.
8.     After the bitstream has been generated, open the implemented design.
9.     In the File menu, click Export -> Export Hardware for SDK, and check all selections.
10.   After SDK has launched, create fsbl and bsp.
11.   Open ps7_init.c in fsbl, and comment every line of EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x80000000U),.
12.   Save ps7_init.c, and compile fsbl again.
13.   Creat a hello world application.
14.   We can generate BOOT.bin with the generated elf files of fsbl and hello world together with the bitstream.
Note: Normally steps 11 and 12 would not  be needed. This is due to the issue described in (Xilinx Answer 61108).

Expected result:

  • Using the Platform USB cable, the user can debug the PL with XILINX tools (e.g., ChipScope)
  • Using a third-party 20-pin header, the user can debug the PS accessing the cortex-A9 CPUs
  • Using a TRACEr, the user can profile the software application

Go to http://www.zedboard.org for more information about the ZED board and the PMOD-7ZJTAG adapter.


文件名 文件大小 File Type
system.xdc 2 KB XDC
ar52095_bd_tcl.tcl 7 KB TCL



Answer Number 问答标题 问题版本 已解决问题的版本
50863 Zynq-7000 AP SoC - 调试 N/A N/A
AR# 52095
日期 06/25/2014
状态 Active
Type 综合文章
  • Zynq-7000
  • Vivado Design Suite - 2014.1