Version Found: MIG 1.7
The MIG Series design sets a DQS_AUTO_RECAL parameter based on the configuration of the core.
This parameter is defined within the module user_design\rtl\phy\mig_7series_v1_7_ddr_byte_lane.v
This parameter is set correctly when using XST, but incorrectly with Synplify.
To work around this issue, modify the setting of the DQS_AUTO_RECAL parameter within the user_design\rtl\phy\mig_7series_v1_7_ddr_byte_lane.v module as follows:
Original Code:localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? 1 : 0;
Modified Code:localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? "1" :" 0";
AR# 52122 | |
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日期 | 08/13/2014 |
状态 | Active |
Type | 已知问题 |
器件 | |
IP |