AR# 52177

描述

Version Found: MIG Virtex-6 and Spartan-6 v3.92
Version Resolved: Not Resolved

The MIG Virtex-6 v3.92 DDR3 VHDL example design might fail timing on the following constraint:

 Timing constraint: TS_c1_u_infrastructure_clk_pll = PERIOD TIMEGRP 
 "c1_u_infrastructure_clk_pll"         TS_sys_clk_f0 / 0.5 HIGH 50%;
 For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 64717 paths analyzed, 22311 endpoints analyzed, 112 failing endpoints
 112 timing errors detected. (112 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   4.336ns.

解决方案

Please use the Verilog generated design as a work-around as this issue only affects MIG Virtex-6 FPGA DDR3 VHDL designs.

Revision History
10/16/2012 - Initial release

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