Version Found: MIG Virtex-6 and Spartan-6 v3.92
Version Resolved: Not Resolved
The MIG Virtex-6 v3.92 DDR3 VHDL example design might fail timing on the following constraint:
Timing constraint: TS_c1_u_infrastructure_clk_pll = PERIOD TIMEGRP
"c1_u_infrastructure_clk_pll" TS_sys_clk_f0 / 0.5 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
64717 paths analyzed, 22311 endpoints analyzed, 112 failing endpoints
112 timing errors detected. (112 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 4.336ns.
Please use the Verilog generated design as a work-around as this issue only affects MIG Virtex-6 FPGA DDR3 VHDL designs.
Revision History
10/16/2012 - Initial release
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
50642 | MIG Virtex-6 and Spartan-6 v3.92 - Release Notes and Known Issues for ISE Design Suite 14.3 | N/A | N/A |
AR# 52177 | |
---|---|
日期 | 08/29/2014 |
状态 | Active |
Type | 已知问题 |
器件 | |
IP |