2. 技术支持
  3. AR# 5218: 1.5i, 2.1i COREGEN : What files are required for proper initialization of a Virtex Block RAM in an HDL behavioral simulation? / What is the MIF file?
  4. AR# 52189: LogiCORE IP G.975.1 EFEC I.7 Encoder/Decoder - Release Notes and Known Issues

AR# 52189

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LogiCORE IP G.975.1 EFEC I.7 Encoder/Decoder - Release Notes and Known Issues

描述

This answer record contains the Release Notes and Known Issues list for theLogiCORE IP G.975.1 EFEC I.7 Encoder/Decoder.

The following information is listed for each version of the core:
  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP G.975.1 EFEC I.7 Encoder/Decoder Product Page:
http://www.xilinx.com/applications/wired-communications/optical-transport-network/index.htm

解决方案

GeneralLogiCORE IP G.975.1 EFEC I.7 Encoder/DecoderIssues

  • N/A

LogiCORE IP G.975.1 EFEC I.7 Encoder/Decoder v1.0

  • Initial release in ISE 14.3 and Vivado 2012.3 tools

Supported Devices (ISE)

  • All Virtex-7 devices
  • All Kintex-7 devices

Supported Devices (Vivado)

  • All Virtex-7 devices
  • All Kintex-7 devices

New Features

  • Initial release
  • OTU2 support (10G)

Resolved Issues

  • N/A

Known Issues (ISE)

  • N/A

Known Issues (Vivado)

  • N/A
AR# 52189
日期 10/03/2012
状态 Active
Type 综合文章
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